Contents
1 Introduction to Power Management . . . . . . . . . .. . . . . . . . . 1
1.1 Low Power Wearable Electronic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Low Power Management Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.1 Dynamic Power Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.2 Leakage Power Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Energy Harvesting-Based Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Aim and Objectives . . . . . . . . . . . . . . . . . . . . . . . . 11
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Introduction to TEG-Based Power Management Unit . . . . . . . . . . . . . . . . . . 15
2.1 Introduction to TEG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Interface Circuit of TEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.1 Startup Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.2 DC–DC Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.3 Maximum Power Point Transfer Techniques . . . . . . . . . . . . . . . . . . 20
2.2.4 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3 Existed TEG-Based Power Management Solutions . . . . . . . . . . . . . . . . . . . 25
References . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 28
3 TEG-Based Power Management Designs and Characterizations . . . . . . 31
3.1 Proposed TEG-Based PMU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.1 Switched Inductor Boost Converter Circuit Design . . . . . . . . . . . 33
3.1.2 Switched Capacitor Regulator Circuit Design. . . . . . . . . . . . . . . . . 33
3.1.3 LDO Regulator Circuit Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2 TEG-Based PMU Measurements in 65 nm CMOS. . . . . . . . . . . . . . . . . . . . 36
3.3 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 46
4 Dual-Outputs Switched Capacitor Voltage Regulator . . . . . . . . . . . . . . . . . . . 47
4.1 State of the Art Dual-Outputs Switched Capacitor Voltage
Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 47
4.2 Proposed Dual-Outputs Switched Capacitor Voltage Regulator . . . . . . 50
4.2.1 Reconfigurable SC Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2.2 ATM Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.3 Clocked Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.4 Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.5 Deadtime Phase Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3 Measured Results of DOSC Regulator in 65 nm CMOS
Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.4 Multi-Outputs Switched Capacitor Voltage Regulator . . . . . . . . . . . . . . . . 67
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Appendix: Verilog Code of ATM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5 Ratioed Logic Comparator-Based Digital LDO Regulator. . . . . . . . . . . . . . 73
5.1 State of the Art Digital LDO Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2 Proposed Ratioed Logic Comparator-Based Digital LDO
Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2.1 Ratioed Logic Comparator-Based DLDO Circuit Design . . . . 78
5.2.2 Enhanced RLC-DLDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3 RLC-DLDO Design Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.4 Simulation Results of RLC-DLDO Regulator in 22 nm FDSOI . . . . . . 87
5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 92
Appendix: Derivation of Output Voltage of the Ratioed Logic Circuit . . . . . 92
Low Output Voltage of Ratioed Logic Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
High Output Voltage of Ratioed Logic Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6 Conclusions and Future Work. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 101
Preface
With the dramatic rise of mobile electronic devices usage especially as an effect of the internet-of-things revolution, the demand for energy efficient and small form factor systems raises the need for low power multisource management unit (PMU) for energy strained devices as well as energy harvesting as alternative power source in many usage scenarios. Energy harvesting becomes one of the pillars that fulfill the needs of ultra-low power devices in many applications including the IoT-based healthcare. Since the harvested energy depends on the availability of various sources from the surroundings, a power management unit (PMU) is required to efficiently regulate the harvested energy.
Power converters and voltage regulators are important building blocks in the PMU in order to interface between the energy harvesting and the system on chip (SoC). Different types of energy harvesting source require different power converters. This depends on the electrical signal obtained from the harvester, harvester size, and efficiency. In addition, the selection of the voltage regulator depends on the area of the whole device and the requirements of various blocks in the SoC such as memory, hardware accelerator, analog front-end, and RF. Hence, sophisticated PMU circuits and techniques are required to enable the development of the state-of-the-art energy harvesting-based PMU including power converters and voltage regulators.
To accomplish this need, this book provides a comprehensive power management circuit design that targets low power wearable electronic devices powered by a thermoelectric generator (TEG) source, a battery or both. This includes extensive literature review about power converters and voltage regulators in addition to experimental results from silicon. This book is organized into 6 chapters. Each chapter carries a brief introduction of the work undertaken and is followed by the detailed circuit, results, and analysis.
Chapter 1 provides detailed background about the power management techniques at technology, circuit, and system level and delivers an overview of the recent energy harvesting source utilized for wearable electronic devices.
Chapter 2 discusses the basic concept of the TEG device and model and how it can harvest the thermal energy based on the Seebeck effect. Further, it provides a comprehensive literature review about the interface circuits required by the TEGbased PMU such as power converters, startup circuits, voltage regulators, and maximum power point tracking technique. In addition, it presents the state-of-theart TEG-based PMU designs that are available in the literature.
Chapter 3 focuses on the characterization of the system level TEG-based PMU using several design options of power converters and voltage regulators. The characterization in terms of power efficiency, voltage ripple, and area are based on measurement results in 65 nm CMOS technology which guides the researchers to select the proper PMU design based on the blocks’ requirements within the device.
Chapter 4 highlights the state-of-the-art multi-outputs switched capacitor voltage regulators. Then, it discusses a dual-outputs switched capacitor (DOSC) voltage regulator using a single switched capacitor design in order to minimize the area of PMU. It highlights how the control circuit of adaptive time multiplexing can be used to generate two output voltage levels and eliminate the reverse current problem. Measurement results are shown in 65nm CMOS technology.
Chapter 5 provides a detailed literature review on the available digital low drop out (LDO) regulator. Then, it introduces a clock-less digital LDO regulator based on a ratioed logic comparator (RLC). Simulation results are shown in 22nm FDSOI technology and a comparison with prior work on digital LDO is illustrated. Finally, Chap. 6 concludes this book and presents possible directions for future work in this area of research.