The FPGA Programming Handbook, Second Edition
Frank Bruno and Guy Eschemann
Table of Contents
Preface xxi
Chapter 1: Introduction to FPGA Architectures 1
Technical requirements ……………………… 2
What is an ASIC? ……………………………….. 2
Why an ASIC or FPGA? • 3
How does a company create a programmable device using an ASIC process? • 5
Introduction to HDLs • 6
Logical versus bitwise operations • 6
Creating gates using HDL • 7
Assign statement (SystemVerilog/Verilog) • 7
Assign statement equivalent (VHDL) • 7
Single line comments • 7
Multiline comments • 7
if statement • 8
Fundamental logic gates • 8
Logical NOT • 8
Logical AND • 9
Logical OR • 10
XOR • 11
More complex operations • 12
Introducing FPGAs ……………………………. 13
Exploring the Xilinx Artix-7 and 7 series devices • 15
Combinational logic blocks • 16
Storage • 17
Clocking • 18
I/Os • 18
DSP48E1 – Xilinx DSP core in 7 series devices • 18
ASMBL architecture • 20
Evaluation boards ……………………………. 20
Nexys A7 100T (or 50T) • 21
Summary ……………………………………….. 22
Questions ……………………………………….. 23
Answers …………………………………………. 23
Further reading ……………………………….. 24
Chapter 2: FPGA Programming Languages and Tools 25
Technical requirements ……………………. 25
Hardware • 25
Information on the Nexys A7 • 26
Software • 26
Hardware Description Languages (HDLs) ………………………………………………………………. 26
SystemVerilog versus Verilog • 27
SystemVerilog versus VHDL • 27
Introducing Vitis and Vivado …………….. 28
Vivado installation • 29
Design flow • 30
Design definition/specification • 30
Design entry/constraints • 31
Simulation • 31
Synthesis • 31
Implementation • 32
Running the example • 33
Loading the design • 33
Directory structure • 38
Testbench • 42
VHDL testbench • 46
Running a simulation • 48
Implementation • 51
Program the board • 54
Summary ……………………………………….. 56
Questions ……………………………………….. 56
Answers …………………………………………. 57
Challenge ……………………………………….. 57
Further reading ……………………………….. 58
Chapter 3: Combinational Logic 59
Technical requirements ……………………. 59
Creating FPGA designs ……………………… 60
How to create reusable code – parameters and generics • 62
Understanding the basics of HDL design ………………………………………………………………… 64
Introducing data types • 65
Creating arrays • 67
Querying arrays • 68
Assigning to arrays • 69
Handling multiple-driven nets • 70
Handling signed and unsigned numbers • 72
Adding bits to a signal by concatenating • 73
Casting signed and unsigned numbers • 74
Creating user-defined types • 74
Accessing signals using values with enumerated types • 75
Packaging up code using functions • 75
Creating combinational logic • 76
Handling assignment operators • 78
Incrementing signals • 79
Making decisions – if-then-else • 79
Introducing the case statement (SystemVerilog) • 82
Using the conditional operator to select data • 83
Introducing the case statement (VHDL) • 84
Using custom data types • 84
Creating structures • 84
Creating unions (SystemVerilog) • 85
Project 2 – Creating combinational logic ………………………………………………………………… 86
Testbench • 87
Simulating using targeted testing • 90
Simulating using randomized testing • 90
Simulating using constrained randomization • 91
Implementing an LOD using the case statement (SystemVerilog) • 91
Controlling implementation using generate • 92
Designing a reusable LOD using a for loop • 94
Setting SELECTOR = DOWN_FOR • 94
Setting SELECTOR = UP_FOR • 95
Counting the number of ones • 96
Implementing an adder/subtractor • 96
Adder • 96
Subtractor • 98
Implementing a Multiplier • 98
Bringing it all together • 100
Adding a latch • 102
Summary ……………………………………… 102
Questions ……………………………………… 103
Answers ……………………………………….. 103
Challenge ……………………………………… 104
Further reading ……………………………… 104
Chapter 4: Counting Button Presses 105
Technical requirements ………………….. 106
What is a sequential element? ………….. 106
Clocking your design • 106
Looking at a basic register • 107
Creating a Flip-Flops using SystemVerilog • 107
Creating a flip-flop using VHDL • 109
When to use always @() for FF generation • 110
Using non-blocking assignments • 111
Registers in the Artix 7 • 114
How to retain state using clock enables • 115
Resetting the FF • 116
Project 3 – Counting Button Presses …… 118
Introducing the seven-segment display • 118
Detecting button presses • 122
Analyzing timing • 123
Looking at asynchronous issues • 124
Using the asynchronous signal directly • 124
Problem with push buttons • 128
Designing a safe implementation • 130
Switching to decimal representation • 132
Introducing the ILA • 134
What about simulation? • 139
Deep dive into synchronization ……….. 140
Why use multiple clocks? • 140
Two-stage synchronizer • 140
Synchronizing control signals • 141
Passing data • 143
Summary ………………………………………. 145
Questions ………………………………………. 145
Answers ……………………………………….. 146
Challenge ………………………………………. 147
Further reading ………………………………. 147
Chapter 5: Let’s Build a Calculator 149
Technical requirements …………………… 149
What is a state machine? …………………. 150
Writing a purely sequential state machine • 150
Splitting combination and sequential logic in a state machine • 152
Designing a calculator interface • 154
Designing a Moore state machine • 156
Implementing a Mealy state machine • 158
Practical state machine design • 161
Project 4 – Building a Simple Calculator ……………………………………………………………….. 161
Packaging for reuse • 161
Coding the top level • 165
Changing frequencies by using a PLL or MMCM • 169
Investigating the divider • 174
Building a non-restoring divider state machine • 175
Simulating the divider • 181
Sizing the intermediate remainder • 182
Project 5 – Keeping cars in line …………. 183
Creating the state diagram • 184
Displaying our traffic lights • 184
Pulse width modulation • 184
Implementing delays with a counter • 186
Summary ……………………………………… 188
Questions ……………………………………… 189
Answers ……………………………………….. 190
Challenge ……………………………………… 190
Extra challenge • 190
Further reading ……………………………… 190
Chapter 6: FPGA Resources and How to Use Them 191
Technical requirements …………………… 192
What is a digital microphone? …………… 192
What is PDM? • 192
Project 6 – Listening and learning ……… 192
Simulating the microphone • 199
Introducing storage • 201
Inferring, instantiating, or using the IP catalog to generate RAM • 201
Basic RAM types • 202
Using xpm_cdc for clock domain crossing • 209
Instantiating memories using xpm_memory • 210
Vivado language templates • 211
Using the IP catalog to create memory • 211
Capturing audio data • 212
Project 7 – Using the temperature sensor ……………………………………………………………… 218
Processing and displaying the data • 220
Smoothing out the data (oversampling) • 222
A deeper dive into FIFOs • 223
Constraints • 227
Generating our FIFO • 227
Summary ……………………………………… 230
Questions ………………………………………. 231
Answers ……………………………………….. 232
Further reading ……………………………… 232
Chapter 7: Math, Parallelism, and Pipelined Design 235
Technical requirements ………………….. 236
Introduction to fixed-point numbers …………………………………………………………………… 236
Project 8 – Using fixed-point arithmetic in our temperature sensor …………………………. 238
Using fixed-point arithmetic to clean up the bring-up time • 238
Temperature conversion using fixed-point arithmetic • 243
What about floating-point numbers? • 250
Floating-point addition and subtraction • 251
Floating-point multiplication • 251
Floating-point reciprocal • 251
A more practical floating-point operation library • 252
A quick look at the AXI streaming interface • 253
Project 9 – Updating the temperature sensor project to a pipelined floating-point
implementation …………………………….. 254
Fixed-to-floating-point conversion • 255
Floating-point math operations • 257
Float-to-fixed-point conversion • 259
Simulation • 260
Simulation environment • 262
Parallel designs ……………………………… 262
ML and AI and massive parallelism • 262
Parallel design – a quick example • 262
Summary ……………………………………… 265
Questions ……………………………………… 265
Answers ……………………………………….. 267
Challenge ……………………………………… 267
Further reading ……………………………… 267
Chapter 8: Introduction to AXI 269
Technical requirements ………………….. 270
AXI streaming interfaces …………………. 270
Project 10 – Creating IP for Vivado using AXI streaming interfaces ……………………………. 271
Seven-segment display streaming interface • 271
Developing the adt7420 IP • 279
Understanding the flt_temp core • 280
Introduction to the IP Integrator • 280
IP Integrator debugging • 296
Packaging the project • 297
AXI4 interfaces (full and AXI-Lite) ……. 298
Developing IPs – AXI-Lite, full, and streaming ………………………………………………………. 302
Adding an unpackaged IP to the IP Integrator • 305
Summary ……………………………………… 308
Questions ……………………………………… 309
Answers ……………………………………….. 310
Completed designs …………………………. 310
Further reading ……………………………… 310
Chapter 9: Lots of Data? MIG and DDR2 311
Technical requirements …………………… 312
Note on VHDL ………………………………… 312
Project 11 – Introducing external memory ……………………………………………………………… 312
Introduction to DDR2 • 312
Generating a DDR2 controller using the Xilinx MIG • 316
Setting AXI parameters • 322
Setting memory options • 322
Defining the FPGA options • 323
Modifying the design for use on the board • 332
Introducing a few other external memory types ……………………………………………………. 338
QDR SRAM • 338
HyperRAM • 339
SPI RAM • 339
Summary ……………………………………… 339
Questions ……………………………………… 340
Answers ………………………………………… 341
Challenge ………………………………………. 341
Further reading ………………………………. 341
Chapter 10: A Better Way to Display – VGA 343
Technical requirements ………………….. 344
Project 12 – Introducing the VGA ………. 344
Defining registers • 349
Coding a simple AXI-Lite interface • 350
Generating timing for the VGA • 352
The VGA monitor timing generator • 357
Displaying text • 360
Requesting memory • 363
Testing the VGA controller • 371
Examining the constraints • 372
Summary ……………………………………… 373
Questions ……………………………………… 373
Answer …………………………………………. 374
Challenge ……………………………………… 375
Further reading ……………………………… 375
Chapter 11: Bringing It All Together 377
Technical requirements …………………… 377
Investigating the keyboard interface …………………………………………………………………… 378
Project 13 – Handling the keyboard …… 385
Testing the PS/2 • 392
Project 14 – Bringing it all together …… 395
Displaying PS/2 keycodes on the VGA screen • 396
Displaying the temperature sensor data • 400
Adding a custom character to the text ROM • 403
Displaying audio data • 404
Summary ……………………………………… 410
Questions ……………………………………… 410
Answers ………………………………………… 411
Challenge ………………………………………. 411
Further reading ………………………………. 411
Chapter 12: Using the PMOD Connectors – SPI and UART 413
Technical requirements ………………….. 414
UART PMOD • 414
ACL2 PMOD • 414
Understanding Peripheral Modules (PMODs) ……………………………………………………….. 414
PMOD Type 1 and 1A • 416
PMOD Type 2 and 2A • 416
PMOD Type 3 and 3A • 417
PMOD Type 4, 5, and 5A • 418
PMOD Type 6 and 6A • 418
PMOD Type 7 and 7A • 419
Introduction to Universal Asynchronous Receiver-Transmitter (UART) ……………………. 420
Bus interface • 420
Waveform • 421
Register interface • 422
RBR – Receive Buffer Register • 423
THR – Transmit Holding Register • 423
IER – Interrupt Enable Register • 423
ISR – Interrupt Status Register • 423
FCR – FIFO Control Register • 424
LCR – Line Control Register • 424
MCR – Modem Control Register • 425
LSR – Line Status Register • 425
MSR – Modem Status Register • 426
SCRATCH – Scratch Pad Register • 426
DLL, DLM – Divisor Register LSB and MSB • 426
UART Implementation • 427
CPU Interface • 427
UART Core • 427
My UART origins • 430
Testing • 430
Simulation • 431
On-board testing • 432
Understanding Serial Peripheral Interface (SPI) ……………………………………………………. 433
ACL2 PMOD • 434
Generic SPI • 435
SPI physical interface • 435
SPI protocol interface • 435
Constructing the SPI • 438
SPI state machine • 438
Summary ……………………………………… 441
Questions ……………………………………… 441
Answers ……………………………………….. 442
Further reading ……………………………… 442
Chapter 13: Embedded Microcontrollers Using the Xilinx MicroBlaze 443
Technical requirements ………………….. 443
Understanding Embedded Microcontrollers …………………………………………………………. 444
Soft vs hard processors • 444
Creating the MicroBlaze project • 445
Block Design • 445
MicroBlaze Peripherals • 451
Exporting the design • 458
The Software Project • 460
GPIOs • 466
Our Software Application • 466
Summary ……………………………………… 472
Questions ……………………………………… 472
Answers ……………………………………….. 473
Challenge ……………………………………… 473
Chapter 14: Advanced Topics 475
Technical requirements ………………….. 476
Exploring more advanced SystemVerilog constructs ………………………………………………. 476
Interfacing components using the interface construct • 476
Using structures • 480
Block labels • 481
Looping using for loops • 482
Looping using do…while • 482
Exiting a loop using disable • 483
Skipping code using continue • 484
Using constants • 484
Packing operators • 485
Indexed part select, +:, -: • 485
Streaming operators • 485
Exploring some more advanced verification constructs ………………………………………….. 487
Introducing SystemVerilog queues • 487
Display formatting enhancements • 489
A quick introduction to assertions • 490
Using $error or $fatal in synthesis • 490
Other gotchas and how to avoid them …………………………………………………………………. 491
Inferring single-bit wires • 491
Bit-width mismatches • 492
Upgrading or downgrading Vivado messages • 492
Handling timing closure • 494
How to pipeline a design • 495
Summary …………………………………….. 500
Questions ……………………………………… 501
Answers ……………………………………….. 502
Further reading ……………………………… 503
Other Books You May Enjoy 507
Index 511